It is the constant endeavor in computer system networks to increase the throughput or rate of data transfer between a host computer and various peripheral devices by use of an efficient I/0 controller which is used to manage these data transfer operations.
It has been characteristic of many prior I/0 controllers that they could only execute one particular data transfer command cycle to completion before commencement of a second data transfer command cycle operation. In a busy system where multiple peripheral units demand attention from the host computer, there were often delay periods before a requesting peripheral unit could manage to get service of the host or where the host was delayed in accessing the I/0 controller to execute data transfers to a selected peripheral unit. By reducing the time delays which prior systems involved, the present I/0 controller, designated as the Small Computer System Interface--Data Link Processor, operates to minimize these time delays and increase throughput.
Peripheral controllers of the type to be described herein have had various of their aspects discussed in prior U.S. patents. Examples of these will be found in U.S. Pat. No. 4,280,193 entitled "Data Link Processor for a Magnetic Tape Data Transfer System"; U.S. Pat. No. 4,613,954. entitled "Block Counter System to Monitor Data Transfers"; and U.S. Pat. No. 4,644,463 entitled "System for Regulating Data Transfer Operations"; U.S. Pat. No. 4,542,457 entitled "Burst Mode Data Block Transfer System"; and U.S. Pat. No. 4,607,348 entitled "Transfer Rate Control System From Tape Peripheral to Buffer Memory of Peripheral Controller". These patents form a background and description of many of the elements and operational functions which go to make up the type of peripheral controllers which are called "data link processors", and these references are deemed to be included herein by reference.